The most relevant prior art known to the inventors includes (1) a number of dynamic memories which have a static column feature (e.g., Intel's I51C65 64k CMOS dynamic memory and a 64k NMOS dynamic memory by Fujitsu); and (2) a "nibble mode" memory access system described in U.S. Pat. No. 4,344,156 (Eaton et al., 1982) and which the inventors believe to be embodied in the INMOS IMS2600P 64k NMOS dynamic memory.
The purpose of the static column feature in dynamic semiconductor memories is to speed access to data in preselected sets of memory locations.
Dynamic memory devices with a static column feature generally operate as follows. Whenever the device receives a row address, a row of data is latched in a set of sense amps. One sense amp is selected when a column address is received. Changes in the column address are detected with an address transition detector circuit and are responded to by generating one or more clock signals which latch the new address into the device's column decoders to select (i.e., transfer the data to the output stage from) one of the sense amps.
The static column feature can speed access to data in a dynamic memory by eliminating the need to explicitly clock in new column addresses. However, the access to data is slowed by the need to detect a change in the column address. The present invention improves on prior versions of the static column data access feature and thereby substantially speeds access to data in small preselected sets of memory locations.
The nibble mode access system of U.S. Pat. No. 4,344,156 (Eaton et al., 1982) represents a different method of achieving high speed access to a small preselected set of memory locations. In the Eaton patent, a series of N decoders and N data latches are provided for sequentially reading or writing data from successive memory loactions. Thus in the Eaton system, the preselected set of memory locations must be accessed in a predetermined unchangeable order. The present invention uses a different system, preferrably used in combination with a static column feature, which allows random access to the preselected set of memory locations. Other differences and advantages of the present invention will be more readily apparent from the following description of the preferred embodiment.
It is therefore a primary object of the invention to provide an improved memory device and particularly a memory device with improved speed of access to data in preselected sets of memory locations.